The present invention relates to a fabrication method of contact windows in semiconductor devices which can efficiently prevent an incomplete silicon exposure of the contact window by sufficient overetching insulators in the contact window formation process.
Recently, as the semiconductor devices have a tendency toward high integration, each device is minimized and the misalignment margin of a photomask is also reduced in a photolithography process. In order to expose fine contact windows, therefore, a self-alignment method is employed in such a manner that a contact window is exposed by using peripheral patterns as an etching mask after forming a larger contact pattern than a necessary contact window. Particularly, a self-alignment method is essential in VLSI memory devices having a design rule below 0.6 .mu.m, a contact size below 0.5 .mu.m, and a misalignment margin below 0.3 .mu.m.
FIG. 1(A) and 1(B) are schematic cross-sectional views each illustrating a conventional fabrication method of contact windows. In FIG. 1(A), a P-type well region 2 is first formed on a P-type substrate 1 and then a switching transistor region is defined by selectively forming a thick field oxide layer 3 on the surface of the P-type well region 2. A P+-type channel stopper 5 to prevent any interaction between two adjacent transistors is formed under the field oxide layer 3 by ion-implantation.
Subsequently, a gate oxide layer 7 is thermally grown on the surface of the P-type well region 2 and polysilicon layers 9 and 10 are sequentially deposited on predetermined positions of the field oxide layer 3 and the gate oxide layer 7 to serve as gate electrodes. The polysilicon layer 9 on a transistor region and the polysilicon layer 10 on the field oxide layer 3 are formed simultaneously.
During this process, a protective oxide layer 11 is left on tops of the polysilicon layers 9 and 10. And then, an oxide layer is deposited over the entire surface and spacers 13 are formed at the side walls of the polysilicon layers 9 and 10 by the a reactive ion etching(RIE) method.
A n-type impurity (phosphorous or arsenic) is implanted into the silicon surfaces 9 and 10 by using the spacer 13 as a impurity blocking layer. Subsequent heat cycles make the impurity diffuse deeper into the P-well region 2 to form a source 15 and a drain 16 of the transistor. Hereinabove, a NMOS transistor is formed on the P-type well, but it can be also formed on a P-type substrate.
Now, referring to FIG. 1(B), after an oxide layer 17 deposited over the entire surface is patterned and etched to expose the diffusion region 15 by the conventional photolithography process. When the diffusion region 15 is exposed, the opening size is larger than the exposed diffusion region 15 and a contact window does not locate completely inside the diffusion region so that the misalignment margin is increased for a self-alignment. The surface of the exposed diffusion region is used as an electrically available region. To guarantee the exposure of the silicon substrate, the oxide layer 17 must be sufficiently overetched since the oxide layer 17 on the polysilicon layers 9 and 10 is also etched away during this etching process.
The protective oxide layer 11 must be made thick enough to maintain sufficient oxide layer thickness after the oxide layer etching process so as to prevent the exposure of the polysilicon layers 9 and 10. Thus, the protective oxide layer 11 must be made thicker than the oxide layer 17. However, the increase of the thickness of the protective oxide layer 11 causes a bad surface topography in a submicron divice level.
In the conventional method of manufacturing the semiconductor devices as described heretofore, the incomplete silicon exposure is prevented by the sufficient overetching after the deposition of the protective oxide layer when a self-aligned contact window is made. But, when the overetching is carried out the exposure of the contact window, the protective oxide layer is also etched away resulting in the exposure of the conductive layer. Furthermore, if the protective oxide layer is deposited excessively thick, the surface topography becomes bad to result in lots of processing difficulties in subsequent steps.